Feature size reduction in microelectronic circuits has been an important contributing factor to the dramatic increase in the processing power of computer arithmetic circuits. However, it is generally accepted that MOS based circuits cannot be reduced further in feature size due to fundamental physical restrictions. Therefore, several emerging technologies are currently being investigated. Nano devices offer greater scaling potential than MOS as well as ultra low power consumption. Nano devices display a switching behaviour that differs from traditional MOS devices. This provides new possibilities and challenges for implementing digital circuits using different techniques like CNTFET,SET, FinFET etc. In this work the design of Inverter and Nand gate using CNT, SET and FinFET has been analyzed elaborately with its own advantageous of the mentioned techniques.

Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.

Many distributed applications require a group of destinations to be coordinated to a single source. Multicasting is a communication paradigm to implement these distributed applications. In multicasting, at least one of the member in the group cannot satisfy the service requirement of the application, the multicast request said to be blocked. On the contrary in manycasting, destinations can join or leave the group, depending upon whether it satisfies the service requirement or not. Manycasting is performed over optical burst-switched (OBS) networks based on multiple qualities of service (QoS) constraints. The multiple constraints can be in the form of physical layer impairments, transmission delay, and reliability of the link. Destinations qualify only if they satisfy the Qos constraints. We develop a simple yet efficient routing algorithm which is based on the classic shortest path algorithm. The proposed layer aware FEC (L-FEC) generates repair symbols so that protection of less important dependency layers can be used with protection of more important layers for combined error correction.

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.

In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are briefly discussed in this paper. Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate. Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. For a Integrated Circuit (IC) perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII. This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip