I.Hameem Shanavas; M. Brindha; V.Nallusamy

An Analogous Computation of Different Techniques for The Digital Implementation of Inverter and NAND Logic Gates

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Author(s)

I.Hameem Shanavas ^1,* M. Brindha ¹ V.Nallusamy ¹

1. Department of ECE, MVJ College of Engineering, Bangalore-560067,India

* Corresponding author.

DOI: https://doi.org/10.5815/ijieeb.2012.04.05

Received: 18 Apr. 2012 / Revised: 12 May 2012 / Accepted: 26 Jun. 2012 / Published: 8 Aug. 2012

Index Terms

CNTFET, SET, FinFET, Inverter and Nand Logic gates

Abstract

Feature size reduction in microelectronic circuits has been an important contributing factor to the dramatic increase in the processing power of computer arithmetic circuits. However, it is generally accepted that MOS based circuits cannot be reduced further in feature size due to fundamental physical restrictions. Therefore, several emerging technologies are currently being investigated. Nano devices offer greater scaling potential than MOS as well as ultra low power consumption. Nano devices display a switching behaviour that differs from traditional MOS devices. This provides new possibilities and challenges for implementing digital circuits using different techniques like CNTFET,SET, FinFET etc. In this work the design of Inverter and Nand gate using CNT, SET and FinFET has been analyzed elaborately with its own advantageous of the mentioned techniques.

Cite This Paper

I.Hameem Shanavas, M.Brindha, V.Nallusamy, "An Analogous Computation of Different Techniques for The Digital Implementation of Inverter and NAND Logic Gates", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.4, no.4, pp.33-38, 2012. DOI:10.5815/ijieeb.2012.04.05

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