International Journal of Information Engineering and Electronic Business(IJIEEB)
ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)
Published By: MECS Press
IJIEEB Vol.4, No.4, Aug. 2012
An Analogous Computation of Different Techniques for The Digital Implementation of Inverter and NAND Logic Gates
Full Text (PDF, 332KB), PP.33-38
Feature size reduction in microelectronic circuits has been an important contributing factor to the dramatic increase in the processing power of computer arithmetic circuits. However, it is generally accepted that MOS based circuits cannot be reduced further in feature size due to fundamental physical restrictions. Therefore, several emerging technologies are currently being investigated. Nano devices offer greater scaling potential than MOS as well as ultra low power consumption. Nano devices display a switching behaviour that differs from traditional MOS devices. This provides new possibilities and challenges for implementing digital circuits using different techniques like CNTFET,SET, FinFET etc. In this work the design of Inverter and Nand gate using CNT, SET and FinFET has been analyzed elaborately with its own advantageous of the mentioned techniques.
Cite This Paper
I.Hameem Shanavas,M.Brindha,V.Nallusamy,"An Analogous Computation of Different Techniques for The Digital Implementation of Inverter and NAND Logic Gates", IJIEEB, vol.4, no.4, pp.33-38, 2012.
Anish Muttreja, Niket Agarwal and Niraj K. Jha,,"CMOS Logic Design with Independent-gate FinFETs",IEEE Transactions,2007
Subhajit Das, Sandip Bhattacharya, Debaprasad Das," Design of Digital Logic Circuits using Carbon Nanotube Field Effect Transistors", International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, December 2011.
Michael C. Wang," Low Power, Area Efficient FinFET Circuit Design", Proceedings of the World Congress on Engineering and Computer Science 2009 Vol I WCECS 2009, October 20-22, 2009, San Francisco, USA
International Technology Roadmap for Semiconductors (ITRS) reports, http://www.itrs.net/reports.html
Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee, "Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects", IEEE Trans. Electron Devices, vol. 56, no. 9, Sep, 2009.
Ali Javey, Jing Guo, Qian Wang, Mark Lundstrom, and Hongjie Dai, "Ballistic carbon nanotube field-effect transistor," Nature, vol. 424, pp. 654-657, 2003.
J. Guo, A. Javey, H. Dai, and M. Lundstrom, "Performance analysis and design optimization of near ballistic carbon nanotube FETs," IEDM Tech. Digest, pp. 703-706, 2004.
R. Saito, G. Dresselhaus, and M. S. Dresselhaus, Physical Properties of Carbon Nanotubes. London: Imperial College Press, 1998.
K. Rathnakannan and P. Vanaja Ranjan ,"Binary Coded Decimal Arithmetic Computation using Single Electron Transistor", International Journal of Nanotechnology and Applications,ISSN 0973-631X Volume 1 Number 2 (2007) pp. 61-72
Michael C. Wang,"Independent-Gate FinFET Circuit Design Methodology", IAENG International Journal of Computer Science, 37:1, IJCS_37_1_06