R.Parthasarathi; P.Karunakaran; S.Venkatraman; T.R.DineshKumar; I.Hameem Shanavas

Design Of High Performance Reconfigurable Routers Using Fpga

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Author(s)

R.Parthasarathi ^1,* P.Karunakaran ¹ S.Venkatraman ² T.R.DineshKumar ² I.Hameem Shanavas ³

1. Department of Electronics & Communication, K.L.N College of Information Technology, Madurai

2. Department of Electronics & Communication, VEL TECH, Avadi

3. Department of Electronics & Communication, M.V.J College of Engineering, Bangalore

* Corresponding author.

DOI: https://doi.org/10.5815/ijieeb.2012.04.07

Received: 17 May 2012 / Revised: 3 Jun. 2012 / Accepted: 1 Jul. 2012 / Published: 8 Aug. 2012

Index Terms

Network-on-chip, Cartesian Network, Router, Verilog HDL, Architecture

Abstract

Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.

Cite This Paper

R.Parthasarathi, P.Karunakaran, S.Venkatraman, T.R.DineshKumar, I.Hameem Shanavas, "Design Of High Performance Reconfigurable Routers Using Fpga", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.4, no.4, pp.46-52, 2012. DOI:10.5815/ijieeb.2012.04.07

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