This paper proposed an algorithm for logic circuits verification using neural networks where a model is built to be trained and tested. The proposed algorithm for combinational circuits' verification is based on merging two of the well-known learning algorithms for neural networks. The first one is the Perceptron Convergence Procedure, which is used for learning the functions of the standard logic gates in order to simulate the whole circuit. While the second is a modified learning algorithm of Back-propagation neural networks to be used for the verification of the hardware design. The algorithm can predict the gates that cause the malfunction in the circuit design.
This work may be considered as a step toward building Distributed Computer Aided Design Environments depending on the parallel processing architecture, particularly in the Neurocomputer architecture.