Work place: K.L.E Dr. M.S.S College of Engineering and Technolgy/E&C, Belagavi, 590008, India
E-mail: arun.tigadi@gmail.com
Website:
Research Interests: Interaction Design, Planning and Scheduling, Computer Architecture and Organization, Operating Systems, Processor Design, Data Structures and Algorithms, Algorithm Design
Biography
Arun S. Tigadi, Assistant professor Department of E and C ,K.L.E DR. M.S.Sheshgiri College of Engineering and Technology. Have a working experience of 9 years in the department of E and C. Received my U.G Degree in E&C from S.D.M CET Dharwad in the year 2006 and P.G Degree in VLSI Design and Embedded systems from K.L.E CET Belagavi in the year 2008.
Fields of interest are Low power VLSI design, FPGA Design, Memory controllers, arbiters, multiport memory design, Real-time system design and Operating systems. Published seven international journal papers and presented three papers in international conferences.
By Arun S Tigadi Hansraj Guhilot
DOI: https://doi.org/10.5815/ijieeb.2018.06.02, Pub. Date: 8 Nov. 2018
The computer memory has been revolutionized in the last 25-30 years, in terms of both capacity and speed of execution. Along with this, even the logic controlling the memory has also become more and more complex and difficult to interface. Usually, memory subsystems will be designed to interact with a single system. Whenever we consider a two system is sharing a common memory, there comes the need for an Arbiter. The major difference between a memory arbiter and a processor scheduler is that the memory arbiter works at a much finer level of granularity. The time taken for the task execution may range from micro to milliseconds, while a RAM controller needs to serve the request in a few nanoseconds. Because of this reason the resource arbiters are usually designed and implemented in hardware rather than in software.
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