International Journal of Information Engineering and Electronic Business (IJIEEB)
IJIEEB Vol. 10, No. 6, 8 Nov. 2018
Cover page and Table of Contents: PDF (size: 1150KB)
Design of an Arbiter for Two Systems Accessing a Single DDR3 Memory on a Reconfigurable Platform
Full Text (PDF, 1150KB), PP.14-20
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Author(s)
Arun S Tigadi
1,*
Hansraj Guhilot
1
Index Terms
Arbiter, memory controller, FPGA(Field programmable gate Array), SDRAM(Synchronous DRAM)
Abstract
The computer memory has been revolutionized in the last 25-30 years, in terms of both capacity and speed of execution. Along with this, even the logic controlling the memory has also become more and more complex and difficult to interface. Usually, memory subsystems will be designed to interact with a single system. Whenever we consider a two system is sharing a common memory, there comes the need for an Arbiter. The major difference between a memory arbiter and a processor scheduler is that the memory arbiter works at a much finer level of granularity. The time taken for the task execution may range from micro to milliseconds, while a RAM controller needs to serve the request in a few nanoseconds. Because of this reason the resource arbiters are usually designed and implemented in hardware rather than in software.
Cite This Paper
Arun S Tigadi, Hansraj Guhilot, "Design of an Arbiter for Two Systems Accessing a Single DDR3 Memory on a Reconfigurable Platform", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol.10, No.6, pp. 14-20, 2018. DOI:10.5815/ijieeb.2018.06.02
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