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V.S.K. Reddy

Work place: Mallareddy college of Engineering and Technology, Secunderabad-500014, India

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Research Interests: Computational Science and Engineering

Biography

S. K. Reddy – Dr. V.S.K. Reddy, Principal, Malla Reddy College of Engineering & Technology was graduated with B.Tech. in Electronics and Communication Engineering (ECE), S.V. University and M.Tech in ECE, JNT University, Hyderabad. He is highly versatile with multidisciplinary specializations in Electronics & Communications and Computers Science & Engineering. He has outstanding contribution with more than 35 Publications in the National and International reputed Conferences and Journals. He is a fellow of IETE, Member of ISTE & Member of IEEE. He was awarded as “Best Teacher” in three consecutive Academic years with citation and cash award. He is the recipient of “India Jewel Award” for outstanding contribution to the research in the field of Engineering and Technology. He is a Member of Board of Studies for M.Tech program at Sreenidhi Institute of Science & Technology, Hyderabad which is in collaboration with M/s. Synopsis-SEER Academy, USA. He is also a member of Board of Studies, ECE & ETM, JNT University, Hyderabad. He is Proactive member in Governing Boards of several engineering colleges.

Author Articles
Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction

By K.Bikshalu V.S.K. Reddy M.V. Manasa K. Venkateswara Rao

DOI: https://doi.org/10.5815/ijem.2014.03.02, Pub. Date: 18 Dec. 2014

Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.

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