International Journal of Engineering and Manufacturing (IJEM)
IJEM Vol. 4, No. 3, 18 Dec. 2014
Cover page and Table of Contents: PDF (size: 413KB)
Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction
Full Text (PDF, 413KB), PP.13-21
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Author(s)
K.Bikshalu
1,*
V.S.K. Reddy
3
M.V. Manasa
2
K. Venkateswara Rao
2
Index Terms
MOSFET, Inverter, NAND gate, Predictive Technology Model, H-Spice Tool, Power dissipation
Abstract
Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.
Cite This Paper
K.Bikshalu, V.S.K. Reddy, M.V. Manasa, K. Venkateswara Rao,"Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction", IJEM, vol.4, no.3, pp.13-21, 2014. DOI: 10.5815/ijem.2014.03.02
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