In recent years, near threshold computing is becoming a promising solution to achieve minimum energy consumption. In this paper, the Dynamic Threshold body MOS (DTMOS) technique is assessed in the context of 10T full subtractor circuit designed to operate in the near threshold region. The performance parameters – Energy, power, area, delay, and EDP were computed and compared with the conventional CMOS (C-CMOS) Full subtractor. The simulations were performed using cadence 90 nm technology with Ultra Low Voltage (ULV) of 0.3V. The results have been shown that the proposed 10T full subtractor circuit with DTMOS scheme achieves more than 18% savings in delay, 26% savings in energy consumption and 39% savings in EDP in comparison with the conventional CMOS configuration and other hybrid counterparts.