Kalpana Sanjay Shete

Work place: Dept. of Electronics BVUCOE Pune, India

E-mail: shete.kalpana4@gmail.com

Website:

Research Interests: Data Structures and Algorithms, Image Processing, Image Manipulation, Image Compression

Biography

Kalpana Shete has received B.E. degree in Electronics and Telecommunication from Pune University, Maharashtra, India in 2011. Now she is pursuing M-Tech Electronics (VLSI) from Bharati Vidyapeeth University College of Engineering, Pune, India. Her research interests include multimedia, digital image processing and VLSI design

Author Articles
Least Significant Bit and Discrete Wavelet Transform Algorithm Realization for Image Steganography Employing FPGA

By Kalpana Sanjay Shete Mangal Patil J. S. Chitode

DOI: https://doi.org/10.5815/ijigsp.2016.06.06, Pub. Date: 8 Jun. 2016

Steganography is the science that deals with conveying secret information by embedding into the cover object invisibly. In steganography, only the authorized party is aware of the existence of the hidden message to achieve secret communication. The image file is mostly used cover medium amongst various digital files such as image, text, audio and video. The proposed idea of this research work is to develop the robust image steganography. It is implemented using Least Significant Bit and Discrete Wavelet Transform techniques for digital image signal to improve the robustness & evaluate the performance of these algorithms. The parameters such as mean square error (MSE), bit error rate (BER), peak signal to noise ratio (PSNR) and processing time are considered here to evaluate the performance of the proposed work. In the proposed system, PSNR and MSE value ranges from 42 to 46 dB and 1.5 to 3.5 for LSB method respectively. For DWT method these results are further improved as it gives higher PSNR values between 49 to 57 dB and lower MSE values 0.2 to 0.7. 

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