Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.

Quantum-Dot Cellular Automata (QCA) is a radical technology, which works at Nanoscale. Due to its numerous advantages over the conventional CMOS-based digital circuits, researchers are now concentrating more on designing digital circuits using this technology. Researchers have reported various findings in this field till now. In this paper, a modular 2:1 Multiplexer has been designed followed by its application in the designing of 1-bit parallel memory. A 4:1 MUX is designed using cascading of two 2:1 multiplexers. This paper also incorporates a comparative analysis of the proposed circuits with some previous designs. This comparison indicates that the designed Multiplexer is showing a considerable reduction in cell count as well as in the area. Here the design and simulation of the circuits are done using QCA Designer Ver. 1.40. Power dissipation simulation analysis of the designed 4:1 multiplexer is also done using QCA Pro tool.