In many classes of applications, mainly in signal and image processing applications, decreasing the static power of computational circuits is a challenge. Multipliers are typically located on the critical path of such systems. A promising approach for energy-efficient design of digital systems is approximate or inexact computing. On the other hand, leakage power and limited scalability become serious obstacles that prevent the continuous miniaturization of the conventional CMOS-based logic circuits. Spin-based devices are considered as promising alternatives for CMOS technology due to their proper characteristics such as near-zero current leakage, sustainability, integrity, low standby power. In this paper a new low power approximate 4-2 compressor is presented which is implemented using spintronic devices. The proposed design is utilized in a multiplier tree for image processing applications. We have simulated and compared the proposed design with state-of-the-art designs in both quantitative and qualitative metrics. The simulation results show that the proposed design has 92% and 188% lower power consumption and PDP, respectively compared to the best state-of-the-art design.

Binary logic circuits are limited by the requirement of interconnections. A feasible solution is to transmit more information over a signal line and utilizing multiple-valued logic (MVL). This paper presents a novel high performance quaternary full adder cell based on carbon nanotube field effect transistor (CNTFET). The proposed Quaternary full adder is designed in multiple valued voltage mode. CNTFET is a promising candidate for replacing MOSFET with some useful properties, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, which make them very appropriate for voltage mode multiple threshold circuits design. The proposed circuit is examined, using Synopsys HSPICE with the standard 32 nm CNTFET technology with different temperatures and supply voltages.