Work place: Department of Electronics and Communciation Engineering, National Institute of Technology Srinagar, Hazratbal 190006, India
E-mail: vipan.kakar@smvdu.ac.in
Website:
Research Interests: Image and Sound Processing, Computer Architecture and Organization
Biography
Vipan Kakkar was born in Amritsar, India, in 1973. He received the B.E. degree in electronics and communication engineering from Nagpur University, India, in 1994 and M.S. degree from Bradford University, UK, in 1997. He received his Ph.D. degree in electronics and communication engineering from Delft University of Technology, Netherlands in 2002. He worked in Research & Development at Phillips, Netherlands as engineer and system architect from 2001 to 2009. Since 2009, he has been an Associate Professor with the Department of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra, India. His research interests include ultra low power analog and mixed signal design, MEMS design, synthesis and optimization of digital circuits, biomedical system and implants design, audio and video processing Dr. Kakkar is a Senior Member IEEE and Life Member IETE and has served as an Executive Member of IEEE and has published many research papers in International Conferences and peer reviewed journals. He has also authored a book on System on Chip Design and has served as an editorial board member of microelectronics and solid state electronics journal
By Bisma Bilal Suhaib Ahmed Vipan Kakkar
DOI: https://doi.org/10.5815/ijem.2018.01.03, Pub. Date: 8 Jan. 2018
CMOS is a technology that has revolutionized the field of electronics. Over the time the processing technologies and design methodologies of CMOS devices have proved to be in full swing with the Moore’s law and the miniaturization paradigm. However, after surviving for more than five decades, CMOS is now facing challenges to live through the submicron ranges. The scaling in CMOS has reached a higher limit, showing adverse effects not only from physical and technological point of view but also from material and economical perspective. This drift inspires the researchers to look for new promising alternatives to CMOS which vow better performance, density and power consumption. One of the promising alternatives to digital designing in CMOS is the Quantum-dot Cellular Automata (QCA). QCA is a technology that involves no current transfer but works on electronic interaction between the cells. The QCA cell basically consists of quantum dots separated by certain distance and the entire transmission of information occurs via the interaction between the electrons localized in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed. Further the building blocks are explained theoretically as well as using QCA Designer implementations with focus on cell interaction and clocking mechanisms.
[...] Read more.By Bisma Bilal Suhaib Ahmed Vipan Kakkar
DOI: https://doi.org/10.5815/ijisa.2017.06.08, Pub. Date: 8 Jun. 2017
The essence of the technology business lies in the improvements and advancements that are continuously taking place in the industry. From vacuum tubes, diodes and transistors to the concepts of nano level designing have by and large created a revolution in the history of mankind. The biggest milestone in this journey has been the CMOS technology which has managed to survive for decades and is still an ongoing research area. However, advancing the technology includes many other dimensions which need to be taken care of. As the devices go on decreasing in size with the improving technology the power dissipation in them becomes a major issue. To counter this, a new logic called reversible logic has come into the pool of research. Further a shift from the transistor based paradigm is being explored to go down to ultra-small structures. A major breakthrough in this can be the Quantum Dot Cellular Automata (QCA) Nanotechnology. In this paper we have given a review about how the reversible logic and QCA nanotechnology together result in ultra-low power designs. Further we have optimized the design of Peres reversible gate using the concepts of explicit interaction of cells in QCA and verified the universal functionality using the optimized designs.
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