Reversible logic has shown considerable acceptance and growth in the research fields like quantum computing, Nano computing and optical computing promising lower power dissipation. This paper proposes an optimised design single-bit reversible comparator called SKAR gate with a purpose of reducing quantum cost. Besides, this novel SKAR gate is used as a single-bit reversible comparator to construct an optimised design for a four-bit reversible comparator. The paper discusses two designs, one with the use of SKAR gate and other one using a derivative gate constructed from SKAR gate. Since the reversible logic aims at reducing the value of its fundamental parameters viz. quantum cost, garbage outputs, ancillary inputs, delay and number of gates; Both the proposed designs for single-bit and four-bit reversible comparator are compared with other existing designs on the basis of elementary parameters of reversible logic.