International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 6, No. 11, 8 Nov. 2014
Cover page and Table of Contents: PDF (size: 422KB)
Designing a Novel Ternary Multiplier Using CNTFET
Full Text (PDF, 422KB), PP.45-51
Views: 0 Downloads: 0
Author(s)
Index Terms
CNTFET, Multi-valued logic (MVL), Multiplier, ternary logic, carbon nanotube.
Abstract
Today, multipliers are included as substantial keys of many systems with high efficiency such as FIR filters, microprocessors and processors of digital signals. The efficiency of the systems are mainly evaluated by their multipliers capability since multipliers are generally the slowest components of a system while occupying the most space.
Multiple Valued Logic reduces the number of the required operations to implement a function and decreases the chip surface. Carbon Nanotube Field Effect Transistors (CNTFET) are considered as good substitutes for Silicon Transistors (MOSFET). Combining the abilities of Carbon Nanotubes Transistors with the advantages of Multiple Valued can provide a unique design which has a higher speed and less complexity.
In this paper, a new multiplier is presented by nanotechnology using a ternary logic that improves the consuming power, raises the speed and decreased the chip surface as well.
The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with other instances.
Cite This Paper
Nooshin Azimi, Hamidreza Hoseini, Abbas Shahsavari, "Designing a Novel Ternary Multiplier Using CNTFET", International Journal of Modern Education and Computer Science (IJMECS), vol.6, no.11, pp.45-51, 2014. DOI:10.5815/ijmecs.2014.11.06
Reference
[1]E. V. Dubova, “Multiple-valued logic in VLSI: challenges and opportunities”, Proceedings of Conference NORCHIP’99, 1999, pp.340-350. Doi:10.1.100.1809.
[2]E. V. Dubrova, “Multiple -Valued Logic in VLSI Design”, International Journal on Multiple -Valued Logic, 2002.
[3]Peiman Keshavarzian and Keivan Navi,"Universal ternary logic circuit design through carbon nanotube technology"Electrical and Computer Engineering Department, Nanoelectronics and Quantum Computing Laboratory of Shahid Beheshti University , 2009. doi:10.1504/IJNT.2009.027557.
[4]Gravati M, Valle M, “Modelling mismatch effects in CMOS translinear loops and current mode multipliers”, In Proc European Conference on Circuit Theory and Design (ECCTD'05), Cork (Ireland),Aug 29 - Sept 1, Vol. III, pp.373-376,2005. doi:10.1109/ECCTD.2005.1523138.
[5]M. Mukaidono .Regular ternary logic functions - ternary logic functions suitable for treating ambiguity. IEEE Trans. Computers .1986; C-35(2):179 - 183.
[6]Jain, A. K., R. J. Bolton and M. H. Abd-El-Barr, "CMOS Multiple-valued Logic Design, Part I: Circuit Implementation", IEEE Transactions on Circuits and Systems-Fundamental Theory and Applications, Vol. 40, No. 8, pp. 503-514, 1993.
[7]Kameyama, M., "Toward the Age of Beyond-Binary Electronics and Systems", Proceedings of 20th IEEE International Symposium on Multiple-Valued Logic, pp. 162-166, 1990.
[8]G. E. Moore, "Cramming more components into integrated circuits," Electronics, vol. 38, 1965.
[9]S. Ijiima, Nature, 354, 56 (1991). http://dx.doi.org/10.1038/354056a0.
[10]P. L. McEuen, M. Fuhrer and H. Park, IEEE T. Nan-otechn. 1, 78 (2002).
[11]Peiman Keshavarzian and Keivan Navi,"Universal ternary logic circuit design through carbon nanotube technology"Electrical and Computer Engineering Department, Nanoelectronics and Quantum Computing Laboratory of Shahid Beheshti University , 2009. doi:10.1504/IJNT.2009.027557.
[12]Raychowdhury A, Roy K, "A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs", ISMVL, Proceedings of the 34th International Symposium on Multiple-Valued Logic, pp. 14-19, 2004.
[13]S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, and P. Avouris, “Carbon Nanotubes as Schottky Barrier Transistors,” Phys. Rev. Lett., vol. 89, no. 10, pp. 1068011-1068014, 2002.
[14]A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai, “High Performance n-Type Carbon Nanotube Field-Effect Transistors with Chemically Doped Contacts,” Nano Lett., vol. 5, no. 2, pp. 345-348, 2005.
[15]Deng J, Wong H.S, "A Compact Model for Carbon Nanotube field-Effect Transistors Including Nonidealities and its Application- Part II: Full Device Model and Circuit Performance Benchmarking," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3195-3205, Dec. 2007.
[16]A. Raychowdhury and K. Roy, IEEE T. Circuits Syst.54, 2391(2007). http://dx.doi.org/10.1109/TCSI. 2007.907799.
[17]A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon and H. Dai, Nanoletter 5, 345 (2005).
[18]Maurizio Valle and Francesco Diotalevi,” An analog CMOS four quadrant current-mode multiplier for low power artificial neural network simplementation”, Department of Biophysical and Electronic Engineering (DIBE), University of Geneva, 2001.
[19]Rasmita Sahoo and R. R. Mishra ,Physics group, Birla Institute of Technology and Science, Pilani, Rajasthan, India "Simulations of Carbon Nanotube Field Effect Transistors", International Journal of Electronic Engineering Research ,2009.
[20]Temel, T.; Morgul, A.; Dept. Of Electr. & Electron. Eng,Bogazici Univ., Istanbul "Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits", 2004.
[21]A.P. Dhande et. Al,"Design and Implementation of 2 Bit Ternary ALU Slice", 3rd International Conference, Sciences of Electronic (SETIT), IEEE Transc., pp.1-11, 2005.
[22]A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, “Logic circuits with carbon nanotube transistors,” Science, vol. 294, no. 5545, pp. 1317–1320, Nov. 2001.
[23]Stanford University CNFET Model website [Online 2008].Available:http://nano.stanford.edu/model.php?id=23.