FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

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Author(s)

Vinod Kapse 1,* Bhavana Jharia 1 S. S. Thakur 2

1. Dept. of Electronics & Communication Engg. Jabalpur Engineering College, Jabalpur, India

2. Dept. of Mathematics, Jabalpur Engineering College, Jabalpur, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijmecs.2012.07.04

Received: 17 Mar. 2012 / Revised: 14 May 2012 / Accepted: 12 Jun. 2012 / Published: 8 Jul. 2012

Index Terms

VLSI, FPGA, Pipelined, Inference Processor, Matching Degree

Abstract

This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The controller is capable of processing fuzzified input. 
The proposed controller is designed for 2-input 1-output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.

Cite This Paper

Vinod Kapse, Bhavana Jharia, S. S. Thakur, "FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller", IJMECS, vol.4, no.7, pp.24-30, 2012. DOI:10.5815/ijmecs.2012.07.04 

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