International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 10, No. 1, 8 Jan. 2018
Cover page and Table of Contents: PDF (size: 813KB)
Design and Analysis of Tunnel FET for Low Power High Performance Applications
Full Text (PDF, 813KB), PP.65-73
Views: 0 Downloads: 0
Author(s)
Umesh Dutta
1,*
M.K.Soni
1
Manisha Pattanaik
2
Index Terms
TFET, Parameter variation, Subthreshold swing, Leakage power, Reliability, Band to Band tunneling, High-K dielectric material, ITRS.
Abstract
Tunnel FET is a promising device to replace MOSFET in low power high performance applications. This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs1-xSbx-InAs) based TFET device. Simulations are performed using TCAD tool and simulation results suggest that conventional DGTFET device has less on current and degraded subthreshold slope as compared to InAs and III-V semiconductor based TFET device. InAs based TFET device provides steep subthreshold slope of 61 mV/dec and off current of the order of nano-amperes at sub 1V operation thereby making it an ideal choice for low power high performance applications. The variation in the performance of the III-V HTFET device with the variation in the mole fraction is also studied in detail. Carefully choosing the mole fraction value in III-V semiconductor based HTFET device can lead to better device performance.
Cite This Paper
Umesh Dutta, M.K.Soni, Manisha Pattanaik, "Design and Analysis of Tunnel FET for Low Power High Performance Applications", International Journal of Modern Education and Computer Science(IJMECS), Vol.10, No.1, pp. 65-73, 2018.DOI: 10.5815/ijmecs.2018.01.07
Reference
[1] B. F. Richard, and W. W. Hayden, “ Zener and Avalanche Breakdown in As- Implanted Low-Voltage Si n-p Junctions,” IEEE Trans. on Electron Devices, vol. 23, no.5, pp.512-518, May 1976.
[2] K. Boucart, and A. M. Ionescu, “Double-Gate Tunnel FET With High-k Gate Dielectric,” IEEE Trans. on Electron Devices, vol. 54, no. 7,pp. 1725-1733, Jul. 2007.
[3] R. Jhaveri, V. Nagavarapu, and J.C.S. Woo, “ Effect of Pocket Doping and Annealing Schemes on the Source- Pocket Tunnel Field- Effect Transistor,” IEEE Trans. on Electron Devices, vol. 58, no. 1, pp. 80-86, Jan. 2011.
[4] H. Liu, S. Dutta, III-V Tunnel FET model manual, 2015, [online] Available: https://nanohub.org/publications/12/2.
[5] L.Lattanzio,D. L. Michielis, and A.M. Ionescu, “Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current,” IEEE Solid-State Dev. Research Conference (ESSDERC), pp. 259-262, 2011, Sept. 2011.
[6] R. Asra, M. Shrivastava, K. VRM Murali, R. K. Pandey, H. Gossner, and V. R. Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS – Comparable Performance,” IEEE Trans. on Electron Devices, vol. 58, no. 7, pp. 1855-1863, Jul. 2011.
[7] R. Jhaveri, V. Nagavarapu, and J. C. S. Woo, “ Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed- Mode Applications,” IEEE Trans. on Electron Devices, vol.56, no.1, pp.93-99, Jan.2009.
[8] A. Mishra, K.K. Jha, M. Pattanaik, “ Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode,” Microelectronics Journal, vol. 45, no. 11, pp. 1515-1521, Nov. 2014.
[9] G. Zhou, L. Yeqing, L. Rui, Z. Qin, S. H. Wan, L. Qingmin, V. Tim, et al. “Vertical InGaAs/InP tunnel FETs with tunneling normal to the gate,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1516-1518, Nov. 2011.
[10] S. Sant, and A. Schenk, “Methods to enhance the Performance of InGaAs/InP Heterojunction Tunnel FET’s,” IEEE Trans. on Electron Devices, vol. 63, no.5, pp. 2169-2175, May 2016.
[11] S. Agarwal, G. Klimeck, and M. Luisier, “Leakage- Reduction Design Concepts for Low-Power Vertical Tunneling Field- Effect Transistors,” IEEE Electron Device Letters, vol. 31, no. 6, pp. 621-623, Jun. 2010.
[12] M. K. Z. Ansari, S. Ahish, D. Sharma, M. H. Vasantha, and YB Nithin Kumar, “Performance analysis of a novel hetero-junction tunnel FET based SRAM at 0.3 V supply voltage,” IEEE Technology Symposium (TechSym), pp. 224-228, Sep. 2016.
[13] S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett,A. Ali, T. Mayer, V. Narayanan, D. Schlom,A. Liu, and S. Datta, “ Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications,” IEEE Electron Devices Meeting (IEDM), pp.1-3, Dec. 2009.
[14] Kim, S.H., Kam, H., Hu, C. and Liu, T.J.K. “Germanium-source tunnel field effect transistors with record high I ON/I OFF,” IEEE VLSI Technology, 2009 Symposium IEEE, pp. 178-179, Jun. 2009.
[15] Z, Qin, W. Zhao, and A. Seabaugh, “Low-subthreshold-swing tunnel transistors,” IEEE Electron Device Letters., vol. 2, no. 4, pp. 297-300, Apr. 2006.
[16] A. C. Seabaugh, and Q. Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.
[17] K-H. Kao, S. V. Anne, G. V. William, S. Bart, G. Guido, and D. M. Kristin “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. on Electron Devices, vol. 59, no. 2, pp. 292-301, Feb. 2012.
[18] V. Saripalli, S. Datta, V. Narayanan, and J. P. Kulkarni, “Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design,” IEEE/ACM International Symposium on Nanoscale Architectures, pp. 45-52, Jun. 2011.
[19] S. Dutta, H. Liu, and V. Naraynan,“Tunnel FET Technology: A reliability perspective,” Microelectronics Reliability, vol. 54, no. 5, pp. 861-874, May 2014.
[20] J. Franco, A. Alian, A. Vandooren, A. S. Verhulst, D. Linten, N. Collaert, and A. Thean, “Intrinsic robustness of TFET subthreshold swing to interface and oxide traps: A comparative PBTI study of InGaAs TFETs and MOSFETs,” IEEE Electron Device Letters, vol. 37, no. 8,pp. 1055-1058, Aug. 2016.
[21] A. Mishra, R. Narang, M. Saxena, and M. Gupta, “Impact of Interfacial Fixed Charges on the Electrical Characteristics of Pocket-Doped Double-Gate Tunnel FET,” IEEE Trans. on Device and Materials Reliability,vol. 16, no. 2, pp. 117-122, Jun. 2016.
[22] W. Cao, C. J. Yao, G. F. Jiao, D. Huang, H. Y. Yu and M. F. Li, “Improvement in Reliability of Tunneling Field-Effect Transistor With p-n-i-n Structure,” IEEE Trans. on Electron Devices, vol. 58, no. 7, pp. 2122-2126, Jul. 2011.
[23] C. Ning, L. Renrong, W. Jing, Z. Wei, and X Jun, “A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics,” Journal of Semiconductors, vol. 33, no. 8, pp.084004-1-084004-6, Aug.2012.
[24] C. Anghel, Hraziia, A. Gupta, A. Amara and A. Vladimirescu,“30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current,” IEEE Trans. on Electron Devices, vol. 58, no. 6, pp. 1649-1654, Jun. 2011.
[25] D. B. Abdi, and M. Jagadesh Kumar, “Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain,” IEEE Journal of the Electron Devices Society, vol. 2, no. 6, pp. 187-190, Nov. 2014.
[26] M. J. Kumar, and S. Janardhanan, “ Doping-less Tunnel Field Effect Transistor: Design and Investigation,” IEEE Trans. on Electron Devices., vol. 60, no. 10, pp. 3285-3290, Oct. 2013.
[27] J. Singh, K. Ramakrishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan, and D. Pradhan, “A novel si-tunnel FET based SRAM design for ultra low-power 0.3 VV DD applications,” IEEE Proceedings Asia and South Pacific Design Automation Conference, pp. 181-186, Jan. 2010.
[28] T.Waho, S.Ogawa and S.Maruyama, “GaAs1-xSbx (0.3< x< 0.9) grown by molecular beam epitaxy,” Japanese Journal of Applied Physics, vol.16, no.10, pp.1875-1876, Oct. 1977.
[29] Pandey, Rahul, Saurabh Mookerjea, and Suman Datta, “Opportunities and Challenges of Tunnel FETs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, no.12, pp.2128-2138, Dec. 2016.
[30] Navlakha N, Lin JT, Kranti A, “Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM,” IEEE Transactions on Electron Devices, vol.64, no.4, pp.1561-1567, April 2017.
[31] Safa S, Noor SL, Khan ZR, “Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure,” IEEE Transactions on Electron Devices, vol. 64, no.4, pp. 1449-1454, April 2017.