International Journal of Image, Graphics and Signal Processing (IJIGSP)
IJIGSP Vol. 4, No. 9, 8 Sep. 2012
Cover page and Table of Contents: PDF (size: 1084KB)
Effective Reverse Converter for General Three Moduli Set{(2^n)-1,(2^n)+1,(2^(pn+1))-1}
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Author(s)
Index Terms
Reverse Converter, Moduli Set, Dynamic Range, Residue Number System
Abstract
Residue number system is a non¬-weighted integer number system which uses the residues of division of ordinary numbers by some modules for representing that ordinary numbers. In this paper, the general three moduli set {(2^n)-1,(2^n)+1,(2^(pn+1))-1} based on CRT algorithm is proposed in which “p” is an even number greater than zero. The special case of this set for p=2 which is {(2^n)-1,(2^n)+1,(2^(pn+1))-1} is also described in this paper. Since the dynamic range of this set is odd, some difficult problems in RNS can be easily solved based on this set using parity checking. The proposed reverse converter is better in speed and hardware in comparison to reverse converters in similar dynamic range. Moreover, from the complexity point of view, the internal arithmetic circuits of this moduli set is improved and is less complex than the other sets in similar dynamic range.
Cite This Paper
Mehdi Hosseinzadeh,Keihaneh Kia,"Effective Reverse Converter for General Three Moduli Set{(2^n)-1,(2^n)+1,(2^(pn+1))-1}", IJIGSP, vol.4, no.9, pp.37-43, 2012. DOI: 10.5815/ijigsp.2012.09.06
Reference
[1]A. Omondi, B. Premkumar. Residue Number Systems: Theory and Implementation. London: Imperial College Press, 2007.
[2]B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs. New York: Oxford University Press, 2000.
[3]G. C. Cardarilli, A. Nannarelli, M. Re. Residue Number System for Low-Power Dsp Applications. In Proc. 41nd Asilomar Conf. Signals Syst. Comput, 2007, 1412–1416.
[4]R. Conway, J. Nelson. Improved RNS Fir Filter Architectures. IEEE Trans. Circuits Syst. Exp. Briefs, 2004, 51(1):26–28.
[5]W. Wang, M. N. S. Swamy, M. O. Ahmad. RNS Application for Digital Image Processing. In Proc. 4th IEEE Int. Workshop System-On-Chip for Real Time Appl.. 2004:77–80.
[6]M. H. Sheu, S. H. Lin, C. Chen, S. W. Yang. An Efficient VLSI Design For A Residue To Binary Converter For General Balance Moduli} 2n-1,2n-3,2n+3,2n+1{. IEEE Transactions Circuits System II: Express Briefs, 2004, 51(2):152-155.
[7]W. Zhang , P. Siy. An Efficient Design Of Residue to Binary Converter for Four Moduli Set (2n–1,2n+1, 22n–2, 22n+1–3) Based on New Crt II. Elsevier Journal of Information Sciences, 2008, 178(1):264-279.
[8]W. Wang, M.N.S Swamy, M.O. Ahmad, Y.Wang. A Study of the Residue to Binary Converter for the Three-Moduli Sets. IEEE Transactions on Circuits and Systems I, 2003, 50(2): 235-243.
[9]M.A. Shang, H.U. Jianhao. An Efficient RNS Parity Checker for Moduli Set {2n-1, 2n+1, 22n+1} and Its Applications. Sci China Ser F-Inf Sci, 2008, 51(10):1563-1571.
[10]Y.Wang, X. Song, M. Aboulhamid, H. Shen. Adder Based Residue to Binary Numbers Converters for {2n-1, 2n, 2n+1}. IEEE Trans. Signal Process, 2002, 50(7):1772–1779.
[11]K. A. Gbolagade, R. Chaves, L. Sousa, S.D. Cotofana. An Improved RNS Reverse Converter for the {22n+1−1,2n,2n−1} Moduli Set. IEEE International Symposium on Circuits and Systems, 2010:2103-2106.
[12]A. S. Molahosseini, S. Sezavar, K. Navi. A New Design of Reverse Converter for a Three-Moduli Set. International Symposium on Intelligent Signal Processing and Communication Systems, 2009: 57-60.
[13]L. Kalampoukas, D. Nikolos, C. Efstathiou. High-Speed Parallel-Perfix Modulo 2n-1 Adders. IEEE Transactions on Computers, 2000: 673- 679.
[14]R. Zimmermann. Efficient VlSI Implementation of Modulo (2n+1) Addition and Multiplication. Proceedings of the 14th Symposium on Computer Arithmetic, IEEE, 1999:158-167.
[15]K. Yuan-Ching, L. Su-Hon, S. Ming-Hwa, W. Jia-You. Efficient VlSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+K,2p+1,2p−1,22p+1). IEEE International Symposium on Circuits and Systems, Iscas 2009:437 – 440.
[16]A. S. Molahosseini, K. Navi, F. Teymouri. A New Four-Modulus RNS to Binary Converter. IEEE International Symposium on Circuits and Systems, 2010: 4161-4164.
[17]A. S. Molahosseini, K. Navi, O. Hashemipur, A. Jalali. An Efficient Architecture for Designing Reverse Converters Based on A General Three-Moduli Set. Elsevier Journal of Systems Architecture, 2008, 54(10):929-934.
[18]P.V. Ananda Mohan. New Reverse Converters for The Moduli Set {2n-3,2n-1,2n+1,2n+3}. Elsevier Jurnal of Aeu - International Journal of Electronics and Communications, 2008, 62(9):643-658.
[19]M. Hosseinzadeh, A. Sabbagh, K. Navi. A Fully Parallel Reverse Converter. International Journal of Electrical, Computer and Systems Engineering, 2007, 1( 3):183-187.
[20]K. Navi, A. S. Molahosseini, M. Esmaeildoust. How to Teach Residue Number System to Computer Scientists and Engineers. IEEE Transactions on Education 1,2010.
[21]B. Cao, T. Srikanthan, C.H. Chang. Efficient Reverse Converters for the Four-Moduli Sets {2n–1, 2n, 2n+1, 2n+1–1} and {2n–1, 2n, 2n+1, 2n–1–1}. IEE Proc Comput Digit Tech, 2005, 152:687–96.
[22]A. Dhurkadas. A High Speed Realisation of a Residue to Binary Number System Converter. IEEE Transactions on Cas, Part II, 1998, 45: 446-447.
[23]P.V. Ananda Mohan, A.B. Premkumar. RNS to Binary Converters for Two Four Moduli Sets {2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n+1+1}. IEEE Transactions on Cas, 2007, Part I, 54: 1245-1254.