Design of High-Performance Real-Time Bus in Parallel Processing System

Full Text (PDF, 181KB), PP.10-16

Views: 0 Downloads: 0

Author(s)

Cheng Xin 1,* Zhou Yunfei 1

1. State Key Lab of Digital Manufacturing Equipment & Technology, Huazhong University of Science and Technology, Wuhan, P.R. China

* Corresponding author.

DOI: https://doi.org/10.5815/ijeme.2011.05.02

Received: 10 Aug. 2011 / Revised: 12 Sep. 2011 / Accepted: 18 Oct. 2011 / Published: 29 Nov. 2011

Index Terms

Real-time bus, parallel processing, data exchange, distributed memory

Abstract

Rapid increases in the complexity of algorithms for real-time signal processing applications have made multi-processors parallel processing technology needed. This paper proposes a design of high-performance real-time bus (RTB), based on which distributed shared memory (DSM) mechanism is established to implement data exchange among multiple processors. Adopting DSM mechanism can reduce the software overhead and improve data processing performance significantly. Definition and implementation details of RTB and data transmission model are discussed. Experimental results show the stable data transmission bandwidth is achieved with performance not affected by the increasing number of processors.

Cite This Paper

Cheng Xin,Zhou Yunfei,"Design of High-Performance Real-Time Bus in Parallel Processing System", IJEME, vol.1, no.5, pp.10-16, 2011. DOI: 10.5815/ijeme.2011.05.02

Reference

[1].James Kohout, Alan D. George, A high-performance communication service for parallel computing on distrRTButed DSP systems, Parallel Computing, 2003, 29: 851-878. 

[2].Murphy C W , Harvey D M , Nicolson L J . Low Cost TMS320C4O/ XC6200 Based Reconfigurable Parallel Image Processing Architecture[C]. Proc. of IEE Colloquium on Reconfigurable Systems, Glasgow, U K. 1999: 91-95.

[3].Model 4293 Qctal TMS320C6203 Processor VME Board, http:/ /www.pentek.com.

[4].Aleksandar Milenkovic, Veljko Milutinovic. A performance evaluation of cache injection in bus-based shared memory multiprocessors. Microprocessors and Microsystems, 2002.2(26): 51-61

[5].Ercan Fikret M, Fung Yu-fai, Suleyman Demokan M. Communication in a multi-layer MIMD system for computer vision[J].Journal of Systems Architecture, 2000 , 46 :1349 - 1364.

[6].TMS320C6000 EMIF to External FIFO Interface. Spra 543, 1999

[7].Yan Luxin, Zhang Tianxu, et al. A DSP/FPGA-based parallel architecture for real-time Image processing. Proc .of 6th World Congress on Control and Automation,Dalian, China, 2006: 10022 - 10025.

[8].Pan Fangsheng, Zhao Feng, et al. Implementation of Parallel Signal Processing System Based on FPGA and Multi-DSP. Computer Engineering, 2006, 32(23): 247-249. (in Chinese)

[9].Li Qun, Xie Li, Sun Zhongxin. The techniques and implementation of a distributed shared memory. Computer research & development.1997.5(34) 327-331

[10].Jelica Protit, Milo Tomasevit, and Veljko Milutinovit. Distributed Shared Memory: Concepts and Systems. IEEE Parallel & Distributed Technology, 1996.2(4):63-79

[11].Zhen Fang, Lixin Zhang, John B. Carter, Liqun Cheng, Michael Parker. Fast synchronization on shared-memory multiprocessors: An architectural approach. J. Parallel Distrib. Comput. 65 (2005) 1158 – 1170