Comparative Analysis of Various SRAM Cells with Low Power, High Read Stability and Low Area

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Author(s)

Abhishek Agal 1,* Pardeep 2 Bal Krishan 3

1. M.Tech.(VLSI),G-41 Rajput colony, Subhash nagar, Bhilwara-311001, India

2. M.Tech.(VLSI),W.N. 15, Shiv colony, Safidon-126112, Jind, India

3. M.Tech.(Nanotechnology), Electronics Engineering Department. YMCA UST, Faridabad-121006, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijem.2014.03.01

Received: 23 Aug. 2014 / Revised: 1 Oct. 2014 / Accepted: 13 Nov. 2014 / Published: 18 Dec. 2014

Index Terms

Delay, SRAM cell, SNM, Power Dissipation

Abstract

SRAMs are very important part of today's movable devices like laptops and mobile phones. Different SRAM cells of different number of transistors have their own respective advantages and drawbacks. In this work an attempt has been made to reduce the leakage power by adding some transistors. Each SRAM cell provides an efficient way to reduce the leakage power, but disadvantage of each SRAM cell limit the application of them.
In this paper, the study and transient analysis on four different SRAM cells has been carried out and compared with respect to various parameters like power dissipation, delay and area. The simulation is carried out in 180nm CMOS technology using tanner tools. Layout is carried out using microwind.

Cite This Paper

Abhishek Agal, Pardeep, Bal Krishan,"Comparative Analysis of Various SRAM Cells with Low Power, High Read Stability and Low Area", IJEM, vol.4, no.3, pp.1-12, 2014. DOI: 10.5815/ijem.2014.03.01

Reference

[1]Abhishek Agal, Pardeep, Bal Krishan. 6T SRAM cell: Design and Analysis. IJERA; Volume 4, Issue 3(Version 1); March 2014; pp 574-577.

[2]B. Calhoun & A. Chandrakasan. A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation. JSSC, 2007.

[3]Z. Liu and V. Kursun. High Read Stability and Low Leakage Cache Memory Cell. IEEE Conference, 2007.

[4]R. Aly, M. Faisal and A. Bayoumi. Novel 7T SRAM Cell For Low Power Cache Design. IEEE SoC Conf., 2005.

[5]I. Carlson et.al. A High Density, Low Leakage, 5T SRAM for Embedded Caches. ESSCIRC, 2004.

[6]Ajay Kumar Dadoria, Arjun Singh Yadav C.M Roy. Comparative Analysis of Variable N-T Sram Cells. International Journal of Advanced Research in Computer Science and Software Engineering; Volume 3, Issue 4; April 2013.

[7]Sapna singh, Neha Arora, Meenkshi Suthar, Neha Gupta. Performance evaluation of different SRAM cell structures at different technologies. International Journal of VLSI design& communication systems (VLSICS); vol.3, No.1; February 2012.

[8]Andrei Pavlov, Manoj Sachdev. CMOS SRAM Circuit Design and parametric test in nano-scaled technologies, Process Aware SRAM Design and Test. Springer; 2008.

[9]N. Kim, K. Flautner, D. Blaauw, and T. Mudge. Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.; vol. 12, no. 2; pp. 167–184; Feb. 2004.

[10]K. Kanda, T. Miyazaki, M. K. Sik, H. Kawaguchi, and T. Sakurai. Two orders of magnitude leakage power reduction of low-voltage SRAM's by row-by-row dynamic V control (RRDV) scheme. in Proc. IEEE Int. ASIC/SOC Conf.; Sep. 2002; pp. 381–385.

[11]A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar, and C. Svensson. Bitline leakage equalization for sub-100 nm caches. in Proc. ESSCIRC; 2003; pp. 401–404.

[12]E. Grossar, M. Stucchi, K. Maex, W. Dehaene. Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. IEEE Journal of Solid-State Circuits; vol. 41; pp. 2577 – 2588; Nov. 2006.

[13]Raychowdhury, S. Mukhopadhyay, K. Roy. A feasibility study of subthreshold SRAM across technology generations. Proc. of International Conference on Computer Design; pp. 417-422; October 2005.

[14]N. Yoshinobu, H. Masahi, K. Takayuki, K. Itoh. Review and future prospects of low-voltage RAM circuits. IBM journal of research and development; vol. 47, No. 5/6; pp.525-552; 2003.

[15]Sanjay Singh, Ravi Saini, Anil K. Saini, AS Mandal, Chandra Shekhar, Anil Vohra. Performance Evaluation of Different Memory Components for FPGA based Embedded System Design for Video Processing Application. I.J. Intelligent Systems and Applications; MECS; Nov. 2013; 12; 113-119.