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International Journal of Engineering and Manufacturing(IJEM)

ISSN: 2305-3631 (Print), ISSN: 2306-5982 (Online)

Published By: MECS Press

IJEM Vol.12, No.4, Aug. 2022

Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic

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Author(s)

Hemalatha K N, Sangeetha B G

Index Terms

Constant Inputs, Garbage Outputs, Multiplier Circuits, Reversible logic, Wallace Tree Multiplier, Quantum cost

Abstract

Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology. When building quantum computers, for example, the use of reversible logic is unavoidable. The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit. The multiplication operation is regarded as one of the most crucial in the ALU unit. In this study, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits. The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic. The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.

Cite This Paper

Hemalatha K N, Sangeetha B G, "Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic", International Journal of Engineering and Manufacturing (IJEM), Vol.12, No.4, pp. 29-36, 2022. DOI:10.5815/ijem.2022.04.03

Reference

[1]Landauer, R., “Irreversibility and heat generation in the computational process”, IBM Journal of Research and Development. (5):183–191, 1961.

[2]Bennett, C.H., “Logical reversibility of computation”, IBM Journal of. Research and Development. (17):525–532, 1973.

[3]Peres A, “Reversible logic and quantum computers” Physical Review. (32):3266–3276, 1985.

[4]V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes, “Synthesis of reversible logic circuits” IEEE Trans. Computer. Aided Des. Integer. Circuits Syst, 22(6):710–722, 2003.

[5]Bennett C.H. “Notes on the history of reversible computation”, IBM Journal of Research and Development, (32): 16–23, 1998.

[6]R. Feynman, Quantum Mechanical Computers. Optics News. 1985; (11): 11–20. 

[7]E. Fredkin, T. Toffoli, “Conservative logic”, Int. J. Theory Phys, (21): 219–253, 1982.

[8]C.S. Wallace., “A suggestion for a fast multiplier”, IEEE Transactions on electronic Computers, 14-17, 1964.

[9]Perkowski, M. and P. Kerntopf, “Reversible Logic”, Invited tutorial, Proc. EURO‐MICRO, Warsaw, Sept 2001.

[10]Landauer, Rolf, "Irreversibility and heat generation in the computing process", IBM Journal of Research and Development, 261-269, 2000.

[11]H. Thapliyal, M.B. Srinivas, “Novel reversible TSG gate and its application for designing components of primitive/reversible quantum ALU”, in Proceedings of 5th IEEE International Conference on Information, Communications and Signal Processing, 1425–1429, 2005.

[12]Ehsan Pour Ali Akbar, Majid Haghparast, Keivan Navi, “Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology”, Microelectronics Journal, Elsevier.2011; 73-981, 2011.

[13]Ehsan Pour Ali Akbar, Mohammad Mosleh, “An efficient design for reversible Wallace unsigned multiplier”, Theoretical Computer science, Elsevier.43-52, 2018.

[14]Sithara Ravendran, Pranose J. Edavoor, Y. B. Nithin Kumar, “Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic”, IEEE Access, Vol 9,108119-108130, 2021.

[15]M.S. Islam, M.M. Rahman, Z. Begum, et al., “Fault tolerant reversible logic synthesis: carry look-ahead and carry-skip adders”, International Conference on Advances in Computational Tools for Engineering Applications, 396–401, 2009.

[16]M. Valinataj, M. Mirshekar, H. Jazayeri, “Novel low-cost and fault-tolerant reversible logic adders”, Computer. Electr. Eng, 56–72, 2016.

[17]R.-G. Zhou, Y.-C. Li, M.-Q. Zhang, “Novel designs for fault-tolerant reversible binary coded decimal adders”, Int. J. Electron, 1336–1356, 2014.

[18]Bolhassani, M. Haghparast, “Optimized reversible divider circuit”, Int. J. Innovative Comput. Appl, 13–33, 2016.

[19]Thapliyal Himanshu, M.B. Srinivas, “Novel reversible TSG gate and its application for designing reversible carry look-ahead adder and other adder architectures”, Lecture Notes of Computer Science, Springer-Verlag,775–786, 2005.

[20]A.N. Nagamani and Vinod Kumar Agrawal, “Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors”, Artificial Intelligence and Evolutionary Algorithms in Engineering Systems, Advances in Intelligent Systems and Computing, Springer, 323-330, 2015.