International Journal of Engineering and Manufacturing(IJEM)
ISSN: 2305-3631 (Print), ISSN: 2306-5982 (Online)
Published By: MECS Press
IJEM Vol.12, No.4, Aug. 2022
Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic
Full Text (PDF, 697KB), PP.29-36
Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology. When building quantum computers, for example, the use of reversible logic is unavoidable. The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit. The multiplication operation is regarded as one of the most crucial in the ALU unit. In this study, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits. The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic. The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.
Cite This Paper
Hemalatha K N, Sangeetha B G, "Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic", International Journal of Engineering and Manufacturing (IJEM), Vol.12, No.4, pp. 29-36, 2022. DOI:10.5815/ijem.2022.04.03
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