International Journal of Computer Network and Information Security (IJCNIS)
IJCNIS Vol. 5, No. 1, 8 Jan. 2013
Cover page and Table of Contents: PDF (size: 556KB)
Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA
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Author(s)
Bahram Rashidi
1,*
Bahman Rashidi
2
Index Terms
Rijndael S-box, Combinational logic, Pipelining, FPGA, VHDL
Abstract
In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the AES cryptographic module thus we implement its mathematic equations based on optimized and combinational logic circuits until dynamic power consumption reduced. The complete data path of the S-box algorithm is simulated as a net list of AND, OR, NOT and XOR logic gates, also for increase in speed and maximum operation frequency used 4-stage pipeline in proposed method. The proposed implemented combinational logic based S-box have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. Power is analized using Xilinx XPower analyzer and achieved power consumption is 29 mW in clock frequency of 100 MHz. The results from the Place and Route report indicate that maximum clock frequency is 209.617 MHz.
Cite This Paper
Bahram Rashidi, Bahman Rashidi, "Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA", International Journal of Computer Network and Information Security(IJCNIS), vol.5, no.1, pp.41-48, 2013. DOI:10.5815/ijcnis.2013.01.05
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