The optoelectronic Biswapped-Hyper Hexa-Cell is a recently reported recursive and a symmetrical architecture of Biswapped Family. This symmetrical network has claimed and proved to be advantageous in terms of network diameter, bisection width, minimum node-degree and network cost compared to its counterpart architecture of OTIS family named ‘OTIS Hyper Hexa-Cell’ and traditional grid-based architecture of Biswapped family named ‘Biswapped-Mesh’. In this paper, we present a novel and efficient parallel algorithm for counting sort for sorting distinct numeric values on dh-dimensional Biswapped-Hyper Hexa-Cell optoelectronic network. The parallel algorithm demands 10d_h+12+ log_2⁡〖S_A 〗 electronic and 10 optical moves, where SA is the size of count array: Acip[SA], and SA equals to maximal minus minimal numeric value plus one. On the basis of analysis, it is concluded that proposed algorithm delivers better performance since speedup and efficiency improved for worst case scenario (difference between maximal and minimal data values becomes larger) with the increase of only few communication moves required for sorting.

The biswapped network hyper hexa-cell is recently reported optoelectronic network architecture for delivering excellent performance especially for mapping numerical problems which demands frequent routing and broadcasting. This network contains some important benefits such as smaller diameter, higher bisection width, and lower network’s total and optical cost as compared to counter-part OTIS hyper hexa-cell network. It is also advantageous as compared to the traditional biswapped network mesh containing smaller diameter and higher minimum node degree. In this paper, we present a parallel algorithm for mapping prefix sum of  data elements on a d_h-dimensional biswapped network hyper hexa-cell of processors (assuming each processor contain single data element). It demands total  + 10 intra-cluster (electronic) and 3 inter-cluster (optical) moves.