International Journal of Intelligent Systems and Applications(IJISA)
ISSN: 2074-904X (Print), ISSN: 2074-9058 (Online)
Published By: MECS Press
IJISA Vol.8, No.9, Sep. 2016
VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network
Full Text (PDF, 372KB), PP.22-29
Very large scale integration (VLSI) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT) and 3-Satisfiability (3-SAT) clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit) developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.
Cite This Paper
Mohd Asyraf Mansor, Mohd Shareduwan M. Kasihmuddin, Saratha Sathasivam,"VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network", International Journal of Intelligent Systems and Applications(IJISA), Vol.8, No.9, pp.22-29, 2016. DOI: 10.5815/ijisa.2016.09.03
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