INFORMATION CHANGE THE WORLD

International Journal of Intelligent Systems and Applications(IJISA)

ISSN: 2074-904X (Print), ISSN: 2074-9058 (Online)

Published By: MECS Press

IJISA Vol.8, No.9, Sep. 2016

VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

Full Text (PDF, 372KB), PP.22-29


Views:100   Downloads:4

Author(s)

Mohd Asyraf Mansor, Mohd Shareduwan M. Kasihmuddin, Saratha Sathasivam

Index Terms

VLSI circuit;Hopfield Network;2-Satisfiability;3-Satisfiability;Circuit accuracy;Transistor

Abstract

Very large scale integration (VLSI) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT) and 3-Satisfiability (3-SAT) clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit) developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

Cite This Paper

Mohd Asyraf Mansor, Mohd Shareduwan M. Kasihmuddin, Saratha Sathasivam,"VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network", International Journal of Intelligent Systems and Applications(IJISA), Vol.8, No.9, pp.22-29, 2016. DOI: 10.5815/ijisa.2016.09.03

Reference

[1]S. Sathasivam, Learning in the Recurrent Hopfield Network, Proceedings of the Fifth International Conference on Computer Graphics, Imaging and Visualisation, pp. 323-328, 2008.  

[2]W.A.T. Wan Abdullah, Logic Programming on a Neural Network. Malaysian Journal of computer Science, 9 (1), pp. 1-5, 1993.

[3]S. Sathasivam, Energy Relaxation for Hopfield Network with the New Learning Rule, International Conference on Power Control and Optimization, pp. 1-5, 2009.

[4]M. Velavan, Boltzman Machine and Hyperbolic Activation Function in Higher Order Network, 9 (2), pp. 140-146, 2014.

[5]S. Sathasivam, P.F. Ng, N. Hamadneh, Developing agent based modelling for reverse analysis method, 6 (22), pp. 4281-4288, 2013.

[6]J. F. Hurdle, E. L. Brunvand, L. Josephson, Asynchronous VLSI design for Neural system implementation, VLSI for Neural Networks and Artificial Intelligence, pp. 129-139, 1994.

[7]G. Gopalakrishnan, L. Josephson, Towards Amalgamating the Synchronous and Asynchronous Styles, Proc. TAU 93: Timing Aspect of VLSI, 1993. 

[8]R. Puff, J. Gu, A BDD SAT solver for satisfiability testing: An industrial case study, Annals of Mathematics and Artificial Intelligence, 17 (2), pp. 315-337, 1996.

[9]F. A. Aloul, A. Sagahyroon, Using SAT-Based Techniques in Test Vectors Generation, Journal of Advance in Information Technology, 1 (4), pp. 153-162, 2010.

[10]J. R. burch, E. M. Clarke, D. E. Long, L. McMillan, D. L. Dill, “ Sequential Circuit Verification Using Symbolic Model Checking,” Proceedings of the 27th ACM/IEEE Design Automation Conference, pp. 46-51, 1990.

[11]J. R. Burch, E. M. Clarke, D. E. Long, L. McMillan, D. L. Dill, Symbolic model checking: 10 20 states and beyond, Logic in Computer Science, LICS’90, Proceedings of the  5th Annual IEEE Symposium, pp. 428-439, 1990.

[12]K. J. Lang, Hill Climbing Beats Genetic Search on a Boolean Circuit Synthesis Problem of Koza’s, Proceedings of the 12th International Conference on Machine Learning, pp. 340-343, 2014.

[13]H. S. Jin, H. J. Han, F. Somenzi, Efficient conflict analysis for finding all satisfying assignments of a boolean circuit, in Tools and Algorithms for the Construction and Analysis of Systems, Berlin, Heidelberg: Springer, pp. 287-300, 2005.  

[14]T. A. Junttila, I. Niemela, Towards an efficient tableau method for Boolean circuit satisfiability checking, in Computational Logic-CL 2000, Berlin, Heidelberg: Springer, pp. 553-567, 2000.

[15]A. Cimatti, M. Roveri, Bertoli. P, Conformant planning via symbolic model checking and heuristic search, Artificial Intelligence, 159 (1), pp. 127-206, 2004.

[16]M. Formann, F. Wagner, The VLSI layout problem in various embedding models, Graph- Theortic Concepts in Computer Science, Berlin, Heidelberg: Springer, pp. 130-139, 1990.

[17]J. J. Hopfield, D. W. Tank, Neural computation of decisions in optimization problem, Biological Cybernatics, 52, pp. 141-152, 1985.

[18]G. Pinkas, R. Dechter, Improving energy connectionist energy minimization, Journal of Artificial Intelligence Research, 3, pp. 223-15, 1995.

[19]D. Vilhelm, J. Peter, & W. Magnus, Counting models for 2SAT and 3SAT formulae. Theoretical Computer Science, 332 (1), pp. 265-291, 2005.

[20]R. Rojas, Neural Networks: A Systematic Introduction. Berlin: Springer, 1996.

[21]N. Siddique, H. Adeli, Computational Intelligence Synergies of Fuzzy Logic, Neural Network and Evolutionary Computing. United Kingdom: John Wiley and Sons, 2013.

[22]R.A. Kowalski, Logic for Problem Solving. New York: Elsevier Science Publishing, 1979.

[23]B. Sebastian, H. Pascal and H. Steffen, Connectionist model generation: A first-order approach, Neurocomputing, 71(13), pp. 2420-2432, 2008.

[24]S. Sathasivam, Upgrading Logic Programming in Hopfield Network, Sains Malaysiana, 39, pp. 115-118, 2010.

[25]B. Tobias and K. Walter, An improved deterministic local search algorithm for 3-SAT, Theoretical Computer Science 329, pp. 303-313, 2004.

[26]U. Aiman and N. Asrar, Genetic algorithm based solution to SAT-3 problem, Journal of Computer Sciences and Applications, 3, pp. 33-39, 2015.

[27]S. Haykin, Neural Networks: A Comprehensive Foundation, New York: Macmillan College Publishing, 1999.

[28]J. Gu, Local Search for Satisfiability (SAT) Problem, IEEE Transactions on Systems, Man and Cybernetics, vol. 23 pp. 1108-1129, 1993.

[29]W. Fernandez, Random 2-SAT: Result and Problems, Theoretical Computer Science, 265, pp. 131-146, 2001.

[30]C. Meadm, L. Conway, Introduction to VLSI system, Reading, MA: Addison-Wesley, 1980.

[31]R. R. Schaller, Moore’s law: past, present and future. Spectrum, 34(6), pp. 52-59, 1997.

[32]R. Sethuram and M. Parashar, Ant colony optimization and its application to Boolean satisfiability for digital VLSI circuits, Advanced Computing and Communications, IEEE, pp. 507-512, 2006.

[33]A. D. Pwasong and S. Sathasivam, Forecasting Performance of Random Walk with Drift and Feed Forward Neural Network Models, International Journal of Intelligent System and Application, vol. 23 pp. 49-56, 2015.

[34]P. Whig and S.N. Ahmad, Performance analysis of various readout circuits for monitoring quality of water using analog integrated circuits, International Journal of Intelligent Systems and Applications, 4 (11), pp. 91-98, 2012.

[35]S. Koussoube, R. Noussi and B.O. Konfe, Using Description Logics to specify a Document Synthesis System. International Journal of Intelligent Systems and Applications, 5(3), p.13, 2013.