Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

Full Text (PDF, 516KB), PP.1-9

Views: 0 Downloads: 0

Author(s)

Maede Kaviani 1 Hojjat Sharifi 2,* Mahdi Dolatshahi 1 Keivan Navi 3

1. Islamic Azad University, Najafabad, Esfahan PO BOX: 8514143131, Iran

2. Vali-e-Asr University of Rafsanjan, Rafsanjan PO BOX: 518, Iran

3. Shahid Beheshti University, GC, Tehran PO BOX: 1983963113, Iran

* Corresponding author.

DOI: https://doi.org/10.5815/ijem.2016.01.01

Received: 23 Sep. 2015 / Revised: 2 Nov. 2015 / Accepted: 7 Dec. 2015 / Published: 8 Jan. 2016

Index Terms

Buffer, BiCMOS, High load, Capacitor, Low power, Inverter

Abstract

BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

Cite This Paper

Maede Kaviani, Hojjat Sharifi, Mahdi Dolatshahi, Keivan Navi,"Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor", International Journal of Engineering and Manufacturing(IJEM), Vol.6, No.1, pp.1-9, 2016. DOI: 10.5815/ijem.2016.01.01

Reference

[1] D. Kim, Y. Lee, J. Cai, I. Lauer, L. Chang, S. J. Koester, et al., "Low power circuit design based on heterojunction tunneling transistors (HETTs)," in Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 219-224.

[2] G.Rajeshwari, Anjo.C.A, N.Arun Kumar, "Design of High Speed Array Multiplier using BiCMOS Logic for Driving Large Load", IJCA Proceedings on National Conference on VLSI and Embedded Systems, 2013.

[3] K.-S. Yeo, H.-K. Lee, and M.-A. Do, "A high-speed twin-capacitor BiNMOS (TC-BiNMOS) logic circuit for single battery operation," Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 48, pp. 399-405, 2001.

[4] H. Etemadi, M. F. Dabiri, P. Keshavarzian, and T. Panahi, "Design of CNTFET-Based invertor Inspired BiCMOS Technology."

[5] P. Heydari and R. Mohavavelu, "Design of ultra-high-speed CMOS CML buffers and latches," in Circuits and Systems, 2003. ISCAS'03. Proceedings of the 2003 International Symposium on, 2003, pp. II-208-II-211 vol. 2.

[6] S. H. Embabi, A. Bellaouar, and K. Islam, "A bootstrapped bipolar CMOS (B 2 CMOS) Gate for low-voltage applications," Solid-State Circuits, IEEE Journal of, vol. 30, pp. 47-53, 1995.

[7] P. Heydari, "Design and analysis of low-voltage current-mode logic buffers," in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 293-298.

[8] N. D. A. GHORBAN, K. Navi, and O. Hashemipour, "High Speed Full Swing Current Mode Bicmos Logical Operators," International Journal of Engineering, 2007.

[9] R. Y. Chik and C. A. T. Salama, "Design of a 1.5 V full-swing bootstrapped BiCMOS logic circuit," Solid-State Circuits, IEEE Journal of, vol. 30, pp. 972-978, 1995.

[10] Shebaita, A., & Ismail, Y. (2008). Multiple threshold voltage design scheme for CMOS tapered buffers. Circuits and Systems II: Express Briefs, IEEE Transactions on, 55(1), 21-25.

[11] Sharma, D., & Mehra, R. (2011). Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology. International Journal of Computer Applications, 22(3), 13-18.

[12] Saxena, A., & Kaushik, P. Design of CMOS Tapered Buffer for High Speed and Low Power Applications using 65nm Technology.